Search - sdram controller

[Other resource] ref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031656 | Author: 包盛花 | Hits:

[Other resource] 标准SDR SDRAM控制器参考设计_verilog_lattice

Description: 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
Platform: | Size: 204299 | Author: 陈旭 | Hits:

[Other resource] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2459435 | Author: 陈东平 | Hits:

[Other resource] ref-sdr-sdram-verilog

Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Platform: | Size: 776597 | Author: 汪旭 | Hits:

[Other resource] sdram

Description: sdram控制器这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3806 | Author: 林博 | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437055 | Author: kevin | Hits:

[WEB Code] SDRAM-VHDL

Description: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Platform: | Size: 125439 | Author: 许春明 | Hits:

[Other resource] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 895594 | Author: 姚明 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 通过 UART 读写 SDRAM verilog 源代码通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00：写数据 02：写个数 0011：写地址 1111 2222：写数据，是 16 bit，每写完一个数据，向串口发送 FF 回应；输出： FF FF 01 03 0044 01: 读sdram 03：读的个数 0044: 读的地址输出： xxxx xxxx xxxx sdram 在 0044 0045 0046 处的数据； sdram 使用的是 K4S161622D.pdf 系统时钟 25m，通过 PLL 得到 SDRAM clk 100m sdram controller clk 100m，前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
Platform: | Size: 14336 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
Platform: | Size: 3031040 | Author: jianzi | Hits:

[VHDL-FPGA-Verilog] SDRAM-control

Description: SDRAM控制器的Verilog源代码，主要用于SDR-SDRAM-SDRAM controller
Platform: | Size: 2824192 | Author: 金文超 | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 非常简单好用的SDRAM控制器，使初学者更加容易理解SDRAM的控制的操作，在Quatrtus环境中验证没问题。-SDRAM controller is very simple and easy to make it easier for beginners to understand the operation of the control of SDRAM, the environment in Quatrtus verify no problem.
Platform: | Size: 3365888 | Author: 马召 | Hits:

[VHDL-FPGA-Verilog] SDRAM_CONTROLlER_Modelsim

Description: SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和文档-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
Platform: | Size: 2302976 | Author: 小单 | Hits:

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[Other resource] ref-ddr-sdram-vhdl

[Other resource] 标准SDR SDRAM控制器参考设计_verilog_lattice

[Other resource] sdr sdram controller

[Other resource] ref-sdr-sdram-verilog

[Other resource] sdram

[Other] ref-ddr-sdram-vhdl

[WEB Code] SDRAM-VHDL

[Other resource] very-good-ok-ref-ddr-sdram-verilog

[VHDL-FPGA-Verilog] sdram

[VHDL-FPGA-Verilog] SDRAM

[VHDL-FPGA-Verilog] SDRAM-control

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

[VHDL-FPGA-Verilog] SDRAM

[VHDL-FPGA-Verilog] SDRAM_CONTROLlER_Modelsim

[VHDL-FPGA-Verilog] sdram-controller

[VHDL-FPGA-Verilog] sdr-sdram-controller-source-code

[Software Engineering] byNeyno_

[VHDL-FPGA-Verilog] DDR-SDRAM-controller-verilog-code

[VHDL-FPGA-Verilog] DDR-SDRAM-Controller

[Software Engineering] alter sdr sdram

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